<?xml version="1.0" encoding="UTF-8"?><rss xmlns:dc="http://purl.org/dc/elements/1.1/" version="2.0">
<channel>
<title>SAM</title>
<link>https://sam.ensam.eu:443</link>
<description>The DSpace digital repository system captures, stores, indexes, preserves, and distributes digital research material.</description>
<pubDate xmlns="http://apache.org/cocoon/i18n/2.1">Sun, 14 Jun 2026 10:35:08 GMT</pubDate>
<dc:date>2026-06-14T10:35:08Z</dc:date>
<item>
<title>Error Estimator for Cauer Ladder Network Representation</title>
<link>http://hdl.handle.net/10985/22541</link>
<description>Error Estimator for Cauer Ladder Network Representation
HIRUMA, Shingo; IGARASHI, Hajime; HENNERON, Thomas; CLENET, Stephane
The Cauer Ladder Network (CLN) method enables to construct a reduced based circuit model of analytical or numerical models, e.g. Finite Element (FE) model, under quasistatic approximation. This paper proposes an estimator which provides guaranteed upper bounds of the truncation error due to the CLN method. The error estimator is tested on an analytical model and a Finite Element model to validate the approach.
</description>
<pubDate>Thu, 01 Sep 2022 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://hdl.handle.net/10985/22541</guid>
<dc:date>2022-09-01T00:00:00Z</dc:date>
<dc:creator>HIRUMA, Shingo</dc:creator>
<dc:creator>IGARASHI, Hajime</dc:creator>
<dc:creator>HENNERON, Thomas</dc:creator>
<dc:creator>CLENET, Stephane</dc:creator>
<dc:description>The Cauer Ladder Network (CLN) method enables to construct a reduced based circuit model of analytical or numerical models, e.g. Finite Element (FE) model, under quasistatic approximation. This paper proposes an estimator which provides guaranteed upper bounds of the truncation error due to the CLN method. The error estimator is tested on an analytical model and a Finite Element model to validate the approach.</dc:description>
</item>
<item>
<title>Topology Optimization of Chip Inductor Using Density Method</title>
<link>http://hdl.handle.net/10985/27083</link>
<description>Topology Optimization of Chip Inductor Using Density Method
YIN, Shuli; IGARASHI, Hajime; CLENET, Stephane
This paper proposes a novel methodology of the topology optimization method considering eddy current effects. The method is applied on chip inductors modelled by the Finite Element Method (FEM). Aiming to meet a specified inductance value while minimizing eddy current losses, we employ a density-based approach to construct a continuous material distribution. The derivative of the objective function with respect to the material distribution is obtained using the adjoint variable method, then the material layout is iteratively updated via the L-BFGS-B algorithm. The proposed framework is validated on both single-turn and multi-turn inductor structures, achieving designs that satisfy the target performance within a limited number of iterations. A key innovation of this work lies in the integration of field-circuit coupling into the topology optimization framework, enabling the analysis of inductors under complex coil configurations involving both series and parallel connections. Additionally, we present an original derivation of the sensitivity formulation associated with the inductance value ensuring that the optimized inductance meets the design specification.
</description>
<pubDate>Wed, 01 Jan 2025 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://hdl.handle.net/10985/27083</guid>
<dc:date>2025-01-01T00:00:00Z</dc:date>
<dc:creator>YIN, Shuli</dc:creator>
<dc:creator>IGARASHI, Hajime</dc:creator>
<dc:creator>CLENET, Stephane</dc:creator>
<dc:description>This paper proposes a novel methodology of the topology optimization method considering eddy current effects. The method is applied on chip inductors modelled by the Finite Element Method (FEM). Aiming to meet a specified inductance value while minimizing eddy current losses, we employ a density-based approach to construct a continuous material distribution. The derivative of the objective function with respect to the material distribution is obtained using the adjoint variable method, then the material layout is iteratively updated via the L-BFGS-B algorithm. The proposed framework is validated on both single-turn and multi-turn inductor structures, achieving designs that satisfy the target performance within a limited number of iterations. A key innovation of this work lies in the integration of field-circuit coupling into the topology optimization framework, enabling the analysis of inductors under complex coil configurations involving both series and parallel connections. Additionally, we present an original derivation of the sensitivity formulation associated with the inductance value ensuring that the optimized inductance meets the design specification.</dc:description>
</item>
</channel>
</rss>
