https://sam.ensam.eu:443 The DSpace digital repository system captures, stores, indexes, preserves, and distributes digital research material. Thu, 14 May 2026 11:09:27 GMT 2026-05-14T11:09:27Z http://hdl.handle.net/10985/25421 Flip-chip technology at room temperature: A new design of microtube-based interconnect for improved mechanical and electrical properties DESBORDES, Cloé; PESCI, Raphaël; PIOTROWSKI, Boris; MAILLIART, Olivier; RAPHOZ, Natacha Flip-chip assembly of photonic components can be achieved at room temperature by using 10 μm pitch interconnects made of metallised oxide microtubes inserted into ductile reception pads. In order to reduce the electrical resistance of interconnects and the assembly force required, interconnect design in regard to geometry and materials used are optimised through electrical and mechanical finite elements (FEM) simulations. To reduce electrical resistance, one may increase the metallisation thickness or microtube inner diameter. To minimise the assembly force, reducing the reception pad diameter is recommended. Experiments on silicon (Si) test vehicles are conducted to validate these predictions; they indicate that there is no short circuit, with an effectiveness of 100 %. This is achieved first through the assembly of Al-0.5 %wCu metallised oxide microtubes into Al-0.5 %wCu reception pads, using a force less than 10 mN/interconnect and proved to have a resistance of 230 mΩ. Second, with gold (Au) metallised oxide microtubes in indium (In) pads assembled with a force less than 0.7 mN/ interconnect. Last interconnects have a resistance of 670 mΩ/interconnect and can still be reduced to 500 mΩ by 2 h annealing at 100 ◦C. Tue, 01 Oct 2024 00:00:00 GMT http://hdl.handle.net/10985/25421 2024-10-01T00:00:00Z DESBORDES, Cloé PESCI, Raphaël PIOTROWSKI, Boris MAILLIART, Olivier RAPHOZ, Natacha Flip-chip assembly of photonic components can be achieved at room temperature by using 10 μm pitch interconnects made of metallised oxide microtubes inserted into ductile reception pads. In order to reduce the electrical resistance of interconnects and the assembly force required, interconnect design in regard to geometry and materials used are optimised through electrical and mechanical finite elements (FEM) simulations. To reduce electrical resistance, one may increase the metallisation thickness or microtube inner diameter. To minimise the assembly force, reducing the reception pad diameter is recommended. Experiments on silicon (Si) test vehicles are conducted to validate these predictions; they indicate that there is no short circuit, with an effectiveness of 100 %. This is achieved first through the assembly of Al-0.5 %wCu metallised oxide microtubes into Al-0.5 %wCu reception pads, using a force less than 10 mN/interconnect and proved to have a resistance of 230 mΩ. Second, with gold (Au) metallised oxide microtubes in indium (In) pads assembled with a force less than 0.7 mN/ interconnect. Last interconnects have a resistance of 670 mΩ/interconnect and can still be reduced to 500 mΩ by 2 h annealing at 100 ◦C. http://hdl.handle.net/10985/20195 Simulation and measurement of residual stress and warpage in a HgCdTe-based infrared detector at 100 K DUPERREX, Lucas; LE BOTERF, Pascal; MAILLIART, Olivier; PESCI, Raphaël A thermomechanical analysis on a 320 × 256, 30 μm pitch, middle wave infrared detector operating at 100 K is conducted. The stress induced in the HgCdTe single crystal layer needs to be minimized to avoid electro-optical perturbations and the planarity of the detector has to respect strict optical requirements. The work includes stress determination by X-ray-diffraction (XRD), warpage measurements with laser scanning, analytical calculation and finite-element modelling. The hybridized detector is studied both alone and after being glued to an AlN hosting substrate. The results show that the initial stress in HgCdTe at room temperature is biaxial for all samples, with either tensile or compressive values (±10 MPa), mainly due to the lattice mismatch during epitaxy from CdZnTe. A stress increase of +45 MPa is induced after cooling to 100 K, with a maximum value of 57 MPa. The warpage of the hybridized circuit is then about 2.5 μm and is reduced after being glued to the hosting substrate. Finally, the model is used to extrapolate the behavior of such a detector for larger formats until 2 K2; there is no significant impact on the stress in the HgCdTe layer, but warpage increases proportionally to the squared diagonal of the detector. Fri, 01 Jan 2021 00:00:00 GMT http://hdl.handle.net/10985/20195 2021-01-01T00:00:00Z DUPERREX, Lucas LE BOTERF, Pascal MAILLIART, Olivier PESCI, Raphaël A thermomechanical analysis on a 320 × 256, 30 μm pitch, middle wave infrared detector operating at 100 K is conducted. The stress induced in the HgCdTe single crystal layer needs to be minimized to avoid electro-optical perturbations and the planarity of the detector has to respect strict optical requirements. The work includes stress determination by X-ray-diffraction (XRD), warpage measurements with laser scanning, analytical calculation and finite-element modelling. The hybridized detector is studied both alone and after being glued to an AlN hosting substrate. The results show that the initial stress in HgCdTe at room temperature is biaxial for all samples, with either tensile or compressive values (±10 MPa), mainly due to the lattice mismatch during epitaxy from CdZnTe. A stress increase of +45 MPa is induced after cooling to 100 K, with a maximum value of 57 MPa. The warpage of the hybridized circuit is then about 2.5 μm and is reduced after being glued to the hosting substrate. Finally, the model is used to extrapolate the behavior of such a detector for larger formats until 2 K2; there is no significant impact on the stress in the HgCdTe layer, but warpage increases proportionally to the squared diagonal of the detector.