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Critical clearing time determination and enhancement of grid-forming converters embedding virtual impedance as current limitation algorithm

Article dans une revue avec comité de lecture
Author
QORIA, Taoufik
COLAS, Frédéric
DENIS, Guillaume
301436 Réseau de Transport d'Electricité [Paris] [RTE]
PREVOST, Thibault
301436 Réseau de Transport d'Electricité [Paris] [RTE]
GUILLAUD, Xavier
13338 Laboratoire d’Électrotechnique et d’Électronique de Puissance - ULR 2697 [L2EP]
ccGRUSON, Francois
13338 Laboratoire d’Électrotechnique et d’Électronique de Puissance - ULR 2697 [L2EP]

URI
http://hdl.handle.net/10985/17951
DOI
10.1109/jestpe.2019.2959085
Date
2019
Journal
IEEE Journal of Emerging and Selected Topics in Power Electronics

Abstract

The present paper deals with the post-fault synchronization of a voltage source converter based on the droop control. In case of large disturbances on the grid, the current is limited via current limitation algorithms such as the virtual impedance. During the fault, the power converter internal frequency deviates resulting in a converter angle divergence. Thereby, the system may lose the synchronism after fault clearing and which may lead to instability. Hence, this paper proposes a theoretical approach to explain the dynamic behavior of the grid forming converter subject to a three phase bolted fault. A literal expression of the critical clearing time is defined. Due to the precise analysis of the phenomenon, a simple algorithm can be derived to enhance the transient stability. It is based on adaptive gain included in the droop control. These objectives have been achieved with no external information and without switching from one control to the other. To prove the effectiveness of the developed control, experimental test cases have been performed in different faulted conditions.

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