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Extension des méthodes DFM pour l'industrialisation de produits microélectroniques

Communication sans acte
Author
SHAHZAD, Muhammad Kashif
74240 Laboratoire des sciences pour la conception, l'optimisation et la production [G-SCOP]
TOLLENAERE, Michel
74240 Laboratoire des sciences pour la conception, l'optimisation et la production [G-SCOP]
HUBAC, Stéphane
23639 STMicroelectronics [Crolles] [ST-CROLLES]
ccSIADAT, Ali
107452 Laboratoire de Conception Fabrication Commande [LCFC]

URI
http://hdl.handle.net/10985/6722
Date
2011

Abstract

Résumé - L'industrie des semi-conducteurs (SMI) est caractérisée par de rapides évolutions sur une courte période de temps. Pour maîtriser les temps de développement (Time to Market) et les montées en cadence (Time-to-Volume), le DFM (Design for Manufacturing) a été intégré dès 1980 dans les outils de conception en tant que stratégie d'atteinte des objectifs de rendement. DFM est ainsi devenu un standard industriel pour estimer le rendement et la fabricabilité dès la conception. Cet article propose une méthodologie DFM pour inclure les résultats des mesures géométriques en corrélation avec les résultats des tests électriques, capturant les capabilités process liées aux performances des produits. L'étude de cas sur la modélisation d'interconnexion est réalisée chez un industriel de haut rang et une méthodologie destinée à aligner rapidement les modèles sur la cible des spécifications est proposée. Le BPR (business process reengineering) et IDEF0 sont utilisés pour définir les workflows qui accompagne la méthodologie proposée ; un modèle de données est ainsi mis en oeuvre via un outil destiné aux ingénieurs R&D. Abstract – Semiconductor manufacturing industry (SMI) is characterized by the fastest change in smallest period of time; hence to address time-to-market and time-to-volume challenges, DFM was included in design flow (1980) as a yield enhancement strategy. It has become an industrial standard to assess yield/manufacturability of the design. Test chip is used to validate the geometric stack against resulted specs and models are frozen and distributed to the CAD department for inclusion in design and DFM kits. This paper proposes a DFM methodology to include geometric measurements which could impact significantly electrical test results making it difficult to adapt the target models. It requires site to site mapping on the wafer which is not trivial because wafer center is different than the mask center and the test structures PCS/M (process control/monitoring structure) could be present in the horizontal or vertical scribe lines. A case study on the interconnect modeling is performed in a top ranked SMI and an extended methodology to rapidly align local interconnect models on target the source specs is proposed. BPR (business process reengineering) and IDEF0 are used for analysis and newly proposed methodology along with a data model which is implemented in a tool for R&D engineers.

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